As a result, this is needed to design the flip-flops for lowest power consumption, propagation delay, area, and highest reliability with fault tolerance ability. The performance and fault tolerance ability of the devices are precisely affected by the flip-flops reliability, speed, and power consumption. Today, the flip-flops are widely used for data storage. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system. In the proposed design, we have used an internal dual feedback structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques.
Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard.
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